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MP2884A Datasheet(PDF) 56 Page - Monolithic Power Systems |
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MP2884A Datasheet(HTML) 56 Page - Monolithic Power Systems |
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56 / 107 page  MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID MP2884A Rev. 1.01 www.MonolithicPower.com 56 12/25/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. Bits Bit Name Description 15:12 APPLICATION_REV Application version. “E” is for engineering version, “0” is for production version. 11:8 SILICON_REV Silicon version. "0" indicates R0, "1" indicates R1, and so on. 7:0 FIRMWARE_REV Revision number indicates different firmware configurations. IOUT_OC_WARN_LIMIT (4Ah) This register sets the output current OC warning threshold. Command IOUT_OC_WARN_LIMIT Format Unsigned binary Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w Function x x x x x x IOUT_OC_WARN_LIMIT Bits Bit Name Description 15:10 RESERVED Unused. X indicates that writes are ignored and reads are always 0. 9:0 IOUT_OC_WARN_LIMIT Output current OC warning threshold. If the sensed output current is greater than this threshold, bit[5] of STATUS_IOUT (7Bh) is set. 1A/LSB (TOTAL_CURRENT_RESOLUTION = 0) 2A/LSB (TOTAL_CURRENT_RESOLUTION = 1) MFR_CS_OFFSET1 (4Ch) This register sets the phase-current offset for the current balance loop. Command MFR_CS_OFFSET1 Format Signed binary Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w Function x CS_OS_PHASE4 CS_OS_PHASE3 CS_OS_PHASE2 Bits Bit Name Description 15 RESERVED Unused. X indicates that writes are ignored and reads are always 0. 14:10 CS_OS_PHASE4 Phase 4 current offset. Two’s complement binary format. Bit[14] is the sign bit. 9:5 CS_OS_PHASE3 Phase 3 current offset. Two’s complement binary format. Bit[9] is the sign bit. 4:0 CS_OS_PHASE2 Phase 2 current offset. Two’s complement binary format. Bit[4] is the sign bit. Calculate the phase-current offset with Equation (15): CS_OS_PHASEn = 512 x IOFFSET x KCS x RCS / 1600 (15) Where RCS is the phase current sense resistor (in kΩ), and KCS is the current sense gain of the DrMOS (in µA/A). |
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