RZSLASHT1 datasheet(135/139 Pages) RENESAS

135 / 139 page

R01DS0228EJ0200 Rev.2.00

Page 135 of 139

Jun. 30, 2025

RZ/T1 Group

1.50

Dec. 26, 2018

All

The company name, modified (ARM → Arm)

Features

■ Encoder interfaces (optional): The descriptions and related note 4, added

Section 1 Overview

Table 1.1 Outline of Specifications (1/7): Central processing unit (Cortex-M3): The architecture

type, corrected (Arm v7-R architecture → Arm v7-M architecture)

Table 1.1 Outline of Specifications (1/7): On-chip extended SRAM with ECC: The entry

"Operating frequency", added

Table 1.1 Outline of Specifications (1/7): Operating modes: The description, modified

Table 1.1 Outline of Specifications (2/7): DMAC: Activation sources, modified

Table 1.1 Outline of Specifications (2/7): ELC: The number of event signals, modified

Table 1.1 Outline of Specifications (3/7): TPUa: The descriptions for pulse input/output, PWM

mode, PPG output trigger, event linking, modified

Table 1.1 Outline of Specifications (3/7): MTU3a: The number of counter-input clock signals,

modified; the feature "automatic transfer of register data", deleted; the description of phase-

counting mode, modified

Table 1.1 Outline of Specifications (4/7): CMT: Event linking, modified

Table 1.1 Outline of Specifications (4/7): POE3: Pin names, corrected

Table 1.1 Outline of Specifications (5/7): ETHERC: The description in relation with "1 port",

modified

Table 1.1 Outline of Specifications (6/7): SSI: "programmable word clock", deleted from the clock

to be generated

Table 1.1 Outline of Specifications (6/7): DSMIF: The description in relation with channel,

modified

Table 1.1 Outline of Specifications (7/7): Encoder interfaces: The number of channels and note 6,

added

Figure 1.1 Block Diagram: The number of channels of MTU3a and DSMIF, modified

Table 1.4 Pin Functions (2/7): Pin names, modified (A0 to A25 → A25 to A0, D0 to D31 → D31 to

D0); the "Description" column for RAS# and CAS#, modified

Table 1.4 Pin Functions (3/7): The "Description" column for MTIOC8A to MTIOC8D and for GPTa,

modified

Table 1.4 Pin Functions (4/7): The "Description" column for each TPUa pin, modified

Table 1.4 Pin Functions (5/7): Ethernet controller (ETHERC): ETH0_RXC, ETH1_RXC,

ETH2_RXC: The "I/O" and "Description" columns, modified (I/O → Input, Receive clock I/O pins

→ Receive clock input pins)

Table 1.4 Pin Functions (6/7): The AUDIO_CLK pin, added

2. Electrical Characteristics

Figure 2.1 Power On/Off Sequence: "Timing" table: "―" was added to the "Value (typ)" column for

Nos (3), (4), and (5).

Table 2.3 DC Characteristics (2) [Power Supply] (1 / 2): VIcc when VDD is 300 MHz in normal

operation, modified

Table 2.5 DC Characteristics (4) [USB2.0 USB_RREF Pin]: The "min" column, modified (200Ω

±1% → 200 ±1%); the "Ω" in the "Unit" column, added

Table 2.12 CLKOUT25Mn Timing, modified (CLKOUT25Mn (RMII): Tck → Tck1, CLKOUT25Mn

(MII): Tck → Tck2)

Figure 2.3 CLKOUT25Mn Pin Output Timing 1: Symbols, modified

Figure 2.4 CLKOUT25Mn Pin Output Timing 2: Symbols, modified

Table 2.13 EXTAL Clock Timing: Time value, modified (40.00 + 50 ppm → 40.00 ± 50 ppm)

Table 2.14 XTAL Clock Timing: Time value, modified (40.00 + 50 ppm → 40.00 ± 50 ppm)

Table 2.24 GPTa Timing: The symbol, modified (TOTETW → tGTEW)

102

Table 2.27 RSPIa Timing: Note 4, added

Rev.

Date

Description

Page

Summary

RZ/T1 Datasheet(PDF) 135 Page - Renesas Technology Corp

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