RZSLASHT1 datasheet(136/139 Pages) RENESAS

136 / 139 page

R01DS0228EJ0200 Rev.2.00

Page 136 of 139

Jun. 30, 2025

RZ/T1 Group

1.60

Nov. 30, 2020

All

Registered trademark symbol added (Arm → Arm®)

All

Package name changed (HLQFP → HLFQFP)

Features

Note 3 deleted (renumbering the subsequent note numbers: Note 4 → Note 3, Note 5 → Note 4)

1. Overview

Table 1.1 Outline of Specifications (2 / 7): VIC, NVIC: Peripheral function interrupts: Number of

sources, modified

Table 1.1 Outline of Specifications (3 / 7): TPUa: The footnote number for the number of units,

modified

Table 1.1 Outline of Specifications (4 / 7): IWDTa: The unit of frequency, modified

Figure 1.1 Block Diagram: The number of MTU3a channels, modified

Table 1.4 Pin Functions (3 / 7): MTU3a: The function of pins MTIOC0m to MTIOC8m, modified

Table 1.4 Pin Functions (3 / 7): GPTa: The function of pins GTIOC0A, GTIOC0B to GTIOC3A,

and GTIOC3B, modified

Table 1.4 Pin Functions (5 / 7): ETHERC: The function of pin ETHSWSECOUT, modified

Figure 1.3 Pin Arrangement (176-pin HLFQFP): Note 2 added

2. Electrical Characteristics

Table 2.4 DC Characteristics (3) [Except for USB2.0 Host/Function-Related Pins]

The footnote number added: Three-state leakage current (off state) / 5-V tolerant pins / |ITSI| →

Three-state leakage current (off state) / 5-V tolerant pins*1 / |ITSI|

Table 2.12 CLKOUT25Mn Timing: CLKOUT25Mn (RMII) / CLKOUT25Mn frequency,

CLKOUT25Mn (MII) / CLKOUT25Mn frequency: The max. and min. values modified; index (n = 0

to 2) added

Table 2.17 Bus Timing (2 / 2): The border under "tWTS", deleted

Figure 2.17 SRAM Bus Cycle with Byte Selection (SW = 1 Cycle, HW = 1 Cycle, Asynchronous

External Wait 1 Inserted, BAS = 0 (Write Cycle UB#/LB# Control)): The title modified

Figure 2.18 SRAM Bus Cycle with Byte Selection (SW = 1 Cycle, HW = 1 Cycle, Asynchronous

External Wait 1 Inserted, BAS = 1 (Write Cycle WE# Control)): The title modified

Figure 2.41 TPUa Clock Input Timing: Text modified (TCLK0A to TCLK0D, TCLK1A to TCLK1D

→ TCLKA to TCLKD)

Figure 2.45 POEn# Input Pulse Timing: Index (n = 0, 4, 8, 10), added

103

Figure 2.53 RSPIa Timing (Master, CPHA = 0): Changed to the correct figure

110

Table 2.29 RIICa Timing: Note 4 modified

115

Table 2.32 ETHERC Timing: Index (n = 0 to 2), added

119

Table 2.33 Serial Management Interface: The entries modified (ETHn_MDC, ETHn_MDIO →

ETH_MDC, ETH_MDIO; Note added

123

Table 2.36 On-chip USB High-Speed Characteristics (USB_DP, USB_DM Pin Characteristics):

The header notation modified (Typ → typ)

1.70

May. 20, 2022 Section 1 Overview

10 to 12

Table 1.3 List of Products (1/3), (2/3), (2/3): Product type name, added

1.3 Product type name, added

1.80

Oct. 31, 2023

Features

Package PLBG0320GB-A, added

Section 1 Overview

Table 1.1 Outline of Specifications (7/7): Packages PRBG0320GB-A and PLBG0320GB-A, added

Table 1.3 List of Products (1/3): 320-pin BB package products (R7S910xxxCBB), added

Table 1.3 List of Products (2/3): 320-pin BB package products (R7S910xxxCBB), added

Table 1.3 List of Products (3/3): 320-pin BB package products (R7S910xxxCBB), added

1.3 Product type name: Package type: BB (PLBG0320GB-A), added

Rev.

Date

Description

Page

Summary

RZ/T1 Datasheet(PDF) 136 Page - Renesas Technology Corp

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