AMD-K6-2ESLASH400AMZ datasheet(162/332 Pages) AMD

162 / 332 page

144

Bus Cycles

Chapter 6

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

Burst Writeback

Figure 55 on page 145 shows a burst read followed by a

writeback transaction. The AMD-K6-2E processor initiates

writebacks under the following conditions:

Replacement —If a cache-line fill is initiated for a cache line

currently filled with valid entries, the processor selects a

line for replacement based on a least-recently-used (LRU)

algorithm

for

the

instruction

cache,

and

least-recently-allocated (LRA) algorithm for the data cache.

Before a replacement is made to an L1 data cache line that is

in the Modified state, the modified line is scheduled to be

written back to memory.

Internal Snoop—The processor snoops its instruction cache

during read or write misses to its data cache, and it snoops

its data cache during read misses to its instruction cache.

This snooping is performed to determine whether the same

address is stored in both caches, a situation that implies the

occurrence of self-modifying code. If a snoop hits a data

cache line in the Modified state, the line is written back to

memory before being invalidated.

WBINVD Instruction—When the processor executes a

WBINVD instruction, it writes back all modified lines in the

data cache and then invalidates all lines in both caches.

Cache

Flush—When

the

processor

samples

FLUSH#

asserted, it executes a flush acknowledge special cycle and

writes back all modified lines in the data cache and then

invalidates all lines in both caches.

The processor drives writeback cycles during inquire or cache

flush cycles. The writeback shown in Figure 55 is caused by a

cache-line replacement. The processor completes the burst read

cycle that fills the cache line. Immediately following the burst

read cycle is the burst writeback cycle that represents the

modified line to be written back to memory. D[63:0] are driven

one clock edge after the clock edge on which ADS# is asserted

and are subsequently changed off the clock edge on which each

of the four BRDY# signals of the burst cycle are sampled

asserted.

AMD-K6-2E/400AMZ Datasheet(PDF) 162 Page - Advanced Micro Devices

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