AMD-K6-2ESLASH400AMZ datasheet(188/332 Pages) AMD

188 / 332 page

170

Bus Cycles

Chapter 6

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

6.6

Special Bus Cycles

The AMD-K6-2E processor drives special bus cycles that

include the following:

Stop grant

Flush acknowledge

Cache writeback invalidation

Halt

Cache invalidation

Shutdown

During all special cycles, D/C# = 0, M/IO# = 0, and W/R# = 1.

BE[7:0]# and A[31:3] are driven to differentiate among the

special cycles, as shown in Table 28. (See also Table 23 on

page 132.)

Note that the system logic must return BRDY# in response to all

processor special cycles.

Basic Special Bus

Cycle

Figure 69 on page 171 shows a basic special bus cycle.

The processor drives D/C# = 0, M/IO# = 0, and W/R# = 1 off the

same clock edge that it asserts ADS#.

In this example, BE[7:0]# = FBh and A[31:3] = 0000_0000h,

which indicates that the special cycle is a halt special cycle (See

Table 28). A halt special cycle is generated after the processor

executes the HLT instruction.

Table 28. Encodings for Special Bus Cycles

BE[7:0]#

A[4:3]1

Notes:

1. A[31:5] = 0

Special Bus Cycle

Cause

FBh

10b

Stop Grant

STPCLK# sampled asserted

EFh

00b

Flush Acknowledge

FLUSH# sampled asserted

F7h

00b

Writeback

WBINVD instruction

FBh

00b

Halt

HLT instruction

FDh

00b

Flush

INVD,WBINVD instruction

FEh

00b

Shutdown

Triple fault

AMD-K6-2E/400AMZ Datasheet(PDF) 188 Page - Advanced Micro Devices

AMD-K6-2E/400AMZ Datasheet(HTML) 188 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL