AMD-K6-2ESLASH400AMZ datasheet(222/332 Pages) AMD

222 / 332 page

204

Cache Organization

Chapter 8

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

8.11

Writethrough and Writeback Coherency States

The terms writethrough and writeback apply to two related

concepts in a read-write cache like the AMD-K6-2E processor’s

L1 data cache. The following conditions apply to both the

writethrough and writeback modes:

Memory Writes—A relationship exists between external

memory writes and their concurrence with cache updates:

•

An external memory write that occurs concurrently with

a cache update to the same location is a writethrough.

Writethroughs are driven as single cycles on the bus.

•

An external memory write that occurs after the processor

has modified a cache line is a writeback. Writebacks are

driven as burst cycles on the bus.

Coherency State—A relationship exists between MESI

coherency states and writethrough-writeback coherency

states of lines in the cache as follows:

•

Shared and invalid MESI lines are in writethrough state.

•

Modified and exclusive MESI lines are in writeback state.

8.12

A20M# Masking of Cache Accesses

Although the processor samples A20M# as a level-sensitive

input on every clock edge, it should only be asserted in real

mode. The processor applies the A20M# masking to its tags,

through which all programs access the caches. Therefore,

assertion of A20M# affects all addresses (cache and external

memory), including the following:

Cache-line fills (caused by read misses or write allocates)

Cache writethroughs (caused by write misses or write hits to

lines in the Shared state)

However, A20M# does not mask writebacks or invalidations

caused by the following actions:

Internal snoops

Inquire cycles

The FLUSH# signal

The WBINVD instruction

Writing to the page flush/invalidate register (PFIR)

AMD-K6-2E/400AMZ Datasheet(PDF) 222 Page - Advanced Micro Devices

AMD-K6-2E/400AMZ Datasheet(HTML) 222 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL