AMD-K6-2ESLASH400AMZ datasheet(225/332 Pages) AMD

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Chapter 9

Write Merge Buffer

207

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

Table 37 summarizes the three settings of the EWBEC field for

the EFER register, along with the effect of write ordering and

performance. For more information on the EFER register, see

“Extended Feature Enable Register (EFER)” on page 43.

9.2

Memory Type Range Registers

The AMD-K6-2E processor provides two variable-range Memory

Type Range registers (MTRRs), MTRR0 and MTRR1, each of

which specifies a range of memory. Each range can be defined

as one of the following memory types:

Uncacheable (UC) Memory—Memory read cycles are

sourced directly from the specified memory address and the

processor does not allocate a cache line. Memory write

cycles are targeted at the specified memory address and a

write allocation does not occur.

Write-Combining (WC) Memory—Memory read cycles are

sourced directly from the specified memory address and the

processor does not allocate a cache line. The processor

conditionally combines data from multiple noncacheable

write cycles that are addressed within this range into a

merge buffer. Merging multiple write cycles into a single

write cycle reduces processor bus utilization and processor

stalls, thereby increasing the overall system performance.

This memory type is applicable for linear video frame

buffers.

Table 37. EWBEC Settings

EFER[3]

(GEWBED)

EFER[2]

(SEWBED)

Write Ordering

Performance

0 or 1

None

Best

All except UC/WC

Close-to-Best

All

Slowest

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