AMD-K6-2ESLASH400AMZ datasheet(178/332 Pages) AMD

178 / 332 page

160

Bus Cycles

Chapter 6

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

AHOLD Restriction

When the system logic drives an AHOLD-initiated inquire

cycle, it must assert AHOLD for at least two clocks before it

asserts EADS#. This requirement guarantees the processor

recognizes and responds to the inquire cycle properly. The

processor’s 32 address bus drivers turn on almost immediately

after AHOLD is sampled negated. If the processor switches the

data bus (D[63:0] and DP[7:0]) during a write cycle off the same

clock edge that switches the address bus (A[31:3] and AP), the

processor switches 102 drivers simultaneously, which can lead

to ground-bounce spikes. Therefore, before negating AHOLD,

the following restrictions must be observed by the system logic:

When the system logic negates AHOLD during a write cycle,

it must ensure that AHOLD is not sampled negated on the

clock edge on which BRDY# is sampled asserted (See Figure

64 on page 161).

When the system logic negates AHOLD during a writeback

cycle, it must ensure that AHOLD is not sampled negated on

the clock edge on which ADS# is negated (See Figure 64).

When a write cycle is pipelined into a read cycle, AHOLD

must not be sampled negated on the clock edge after the

clock edge on which the last BRDY# of the read cycle is

sampled asserted. This avoids the processor simultaneously

driving the data bus (for the pending write cycle) and the

address bus off this same clock edge.

AMD-K6-2E/400AMZ Datasheet(PDF) 178 Page - Advanced Micro Devices