RZSLASHT2L datasheet(33/103 Pages) RENESAS

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Table 2.14

IO setting (DRCTLm register setting) condition (2 of 2)

Module

Signal

IO type

Voltage

DRCTLm register

DRVn

SRn

SMTn

Ethernet Interface

(n = 0 to 2)

ETHn_TXCLK, ETHn_TXD[3:0]

—

1.8 V*1/3.3 V

High

Fast

Disable

ETH2_TXER

—

3.3 V

Middle

Fast

—

ETHn_RXCLK, ETHn_RXD[3:0]

—

1.8 V*1/3.3 V

—

Disable

ETHn_RXER, ETH2_COL, ETH2_CRS

—

3.3 V

—

Disable

ETHn_REFCLK, RMIIn_REFCLK

—

3.3 V

High

Fast

—

Other than the above

—

Low

Slow

Disable

SHOSTIF

HSPI_CK, HSPI_CS#, HSPI_IO[7:0]

—

3.3 V

High

Fast

Disable

HSPI_INT#

—

3.3 V

Low

Slow

Disable

Debug Interface

TRACECLK, TRACECTL, TRACEDATA

[7:0], TDO, TMS

—

3.3 V

High

Fast

Disable

Other than the above

—

Low

Slow

Disable

Other than the above

—

Low

Slow

Disable

Note 1. 1.8 V is only supported for xSPI0 and Ethernet port 2 (ETH2_).

2.5.1

Clock Timing

2.5.1.1

CKIO Pin Output Timing

Table 2.15

CKIO pin output timing

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

CKIO pin output cycle time

tCKcyc

Figure 2.2

—

53.4

CKIO pin output high level pulse width tCKH

tCKcyc / 2 − tCKr

—

CKIO pin output low level pulse width

tCKL

tCKcyc / 2 − tCKf

—

CKIO pin output rising time 1

tCKr

CKIO: High drive output

Setting

—

3.8

CKIO pin output falling time 1

tCKf

—

3.8

CKIO pin output rising time 2

tCKr

CKIO: Normal output

setting

—

CKIO pin output falling time 2

tCKf

—

CKIO pin output

tCKcyc

1/2 VCC33

tCKH

tCKL

tCKf

tCKr

VOH33

VOL33

1/2 VCC33

VOL33

VOH33

Figure 2.2

CKIO pin output timing

2.5.1.2

Ethernet PHY Reference Clock Output Timing

Conditions:

C = 30 pF (ETHn_REFCLK)

C = 20 pF (RMIIn_REFCLK)

RZ/T2L Datasheet

2. Electrical Characteristics

R01DS0409EJ0130 Rev.1.30

Feb 27, 2026

Page 33 of 103

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