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RZ/T2L Datasheet(PDF) 18 Page - Renesas Technology Corp |
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RZ/T2L Datasheet(HTML) 18 Page - Renesas Technology Corp |
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18 / 103 page  Table 1.17 Pin functions (7 of 7) Classification Pin name I/O Description Hiperface DSL (HDSL) HSDL0_LINK, HSDL1_LINK Output HDSL LINK HDSL0_SMPL, HDSL1_SMPL Output HDSL Test signal line sampler HDSL0_CLK1, HDSL1_CLK1 Input HDSL SPI clock safe 1 HDSL0_SEL1, HDSL1_SEL1 Input HDSL SPI selection safe 1 HDSL0_MISO1, HDSL1_MISO1 Output HDSL SPI data output safe 1 HDSL0_MOSI1, HDSL1_MOSI1 Input HDSL SPI data input safe 1 HDSL0_CLK2, HDSL1_CLK2 Input HDSL SPI clock safe 2 HDSL0_SEL2, HDSL1_SEL2 Input HDSL SPI selection safe 2 HDSL0_MISO2, HDSL1_MISO2 Output HDSL SPI data output safe 2 HDSL0_MOSI2, HDSL1_MOSI2 Input HDSL SPI data input safe 2 ENCOUT POUTA Output ENCOUT A-phase output pin POUTB Output ENCOUT B-phase output pin POUTZ Output ENCOUT C-phase output pin 1.5 FBGA 196 Pin Assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VSS P01_3 P00_3 P24_1 P22_3 P22_2 P21_6 P21_1 VSS AN100 AN002 AN000 VSS P01_7 P01_5 P01_2 P00_1 P23_7 P21_7 P21_5 P21_2 AN103 AN101 AN001 VSS P18_6 P02_1 P01_6 P01_1 P00_2 P24_2 P22_0 P21_3 P20_3 AN102 AN003 AVCC18_ TSU P18_5 P18_4 P02_3 P02_0 P01_0 P00_6 P24_0 P22_1 P21_4 VCC33 VREFH0 VSS P18_2 P18_3 P18_1 P02_5 P02_2 P02_4 P01_4 P00_0 VCC1833 _2 VDD VDD VCC18_ ADC0 VSS P17_4 P17_7 P18_0 P04_1 P02_7 P02_6 TRST# VCC33 VDD VSS VSS P06_4 P06_2 P06_1 P05_7 VDD VSS VSS VSS VSS VDD P15_6 P15_5 P15_4 P15_7 P06_7 P06_5 P06_6 P06_3 VCC33 VDD VSS VSS VDD VCC1833 _3 P15_3 P15_0 P15_1 P15_2 P07_0 P07_2 P07_3 P07_1 P09_0 VDD VDD VDD VCC33 VCC1833 _3 P14_2 P14_7 P14_4 P14_6 VSS P08_5 P08_4 P09_4 P10_1 VCC33 P07_4 VDD P13_2 P13_3 P13_7 P13_5 P14_3 P14_5 P08_7 P08_6 P09_1 P09_7 P10_2 VSS MDX VCC18_ PLL1 VSS VCC33_ USB VSS_ USB P13_4 P13_6 P14_1 P09_2 P09_3 P09_5 P10_0 RES# EXT CLKIN VSS VCC18_ PLL0 VSS_ USB VSS_ USB AVCC18_ USB VSS_ USB VSS_ USB P14_0 A B C D E F H J K L M N P VSS P09_6 P10_3 P10_4 VSS EXTAL XTAL VSS USB_DM USB_DP VCC18_ USB USB_ RREF VSS_ USB VSS P06_0 P05_6 P05_5 BSCANP VDD VSS VSS VSS VCC33 P17_0 P17_6 P17_3 P17_5 G VSS VDD P16_1 P16_0 P16_2 P16_3 VDD VCC18_ ADC1 VREFH1 VSS VSS P20_4 A B C D E F H J K L M N P G 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Figure 1.2 Pin arrangement (196-pin FBGA) (top view) Table 1.18 List of pins and pin functions (196-pin FBGA) (1 of 8) Pin number I/O power domain Power supply clock system control I/O port Bus, DMAC Timer (MTU3, POE3, GPT / POEG, CMTW, RTC) Communication (SCI, IIC, GMAC, ESC, USB, CANFD, SPI, xSPI) DSMIF, Mailbox Interrupt ADC12 Host interface (SHOST) Encoder I/F A1 — VSS — — — — — — — — — A2 VCC1833_2 — P01_3 AH# MTIOC4D / GTIOC3B ETH2_TXD2 — IRQ2 — — POUTZ RZ/T2L Datasheet 1. Overview R01DS0409EJ0130 Rev.1.30 Feb 27, 2026 Page 18 of 103 |
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