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RZ/T2L Datasheet(PDF) 9 Page - Renesas Technology Corp |
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RZ/T2L Datasheet(HTML) 9 Page - Renesas Technology Corp |
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9 / 103 page ![]() Table 1.12 Security Feature Functional description Security*1 ● Secure boot ● JTAG authentication ● Cryptographic accelerators – Symmetric Cipher: AES 128/192/256 bits with CBC/ECB/CTR/GCM/XTS – Asymmetric Cipher: ECC 256 bits, RSA 1024/2048/3072 bits, RSAES-OAEP – Hash: SHA-1, SHA-2 – Message authentication: HMAC, CMAC, GMAC – Signature algorithms: ECDSA with NIST P-256, RSASSA-PSS, RSASSA-PKCS1 ● TRNG Note 1. For details, contact our sales representative. Table 1.13 Debug Feature Functional description Debugging interface ● CoreSight architecture designed by Arm ● Debugging function by the JTAG/SWD interface, and trace function by the trace port interface Table 1.14 External host interface Feature Functional description Serial host interface (SHOSTIF) ● Serial communication is possible in slave mode. ● Supported interface – Motorola Serial Peripheral Interface (4-wire SPI) – Enhanced SPI Modes with Dual, Quad, or Octal SPI ● Serial clock polarity switching ● Serial clock phase switching ● Single Data Transfer ● Data size is up to 32 bits × 64 burst Mailbox and semaphore (MBXSEM) ● Eight semaphores ● Four 32-bit mailboxes for both external host CPU to Cortex-R52 and Cortex-R52 to external host CPU ● Interrupts can be generated and cleared from both external host CPU and Cortex-R52 Table 1.15 Others Feature Functional description Power supply voltage VDD = 1.1 V (Core) VCC18 = 1.8 V (PLL, USB, ADC, TSU) VCC33 = 3.3 V (I/O, USB) VCC1833 = 1.8 V (RGMII, xSPI) or 3.3 V (RMII/MII, xSPI*1) Operating temperature Tj = −40 to +125°C Packages 196 pin FBGA 12 × 12 mm, 0.8-mm pitch Note 1. Maximum xSPI clock frequency is 75 MHz at 3.3 V. RZ/T2L Datasheet 1. Overview R01DS0409EJ0130 Rev.1.30 Feb 27, 2026 Page 9 of 103 |
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