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RZ/T2L Datasheet(PDF) 61 Page - Renesas Technology Corp |
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RZ/T2L Datasheet(HTML) 61 Page - Renesas Technology Corp |
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61 / 103 page ![]() CKIO tDACD tDACD Tr Tc4 A25 to A0 tAD1 tAD1 tCSD1 tRWD1 A12/A11*1 RD/WR# tCSD1 DACK*2 Tc1 Tc2 tRWD1 D15 to D0 tBSD BS# tBSD Row address Column address tAD1 tAD1 tAD1 WRIT command CS3#, CS2# RAS# tRASD1 tRASD1 tCASD1 CAS# tCASD1 DQMLU, DQMLL tDQMD1 tDQMD1 (High) CKE Tc3 tAD1 tAD1 tAD1 tAD1 tWDH2 tWDD2 tRWD1 tWDH2 tWDD2 tRASD1 tRASD1 tRWD1 tAD1 Tpw Tp Note 1. Address pin to be connected to A10 of SDRAM. Note 2. DACK is waveform when active-low is specified. Figure 2.32 Synchronous DRAM burst-write bus cycle (write for 4 cycles) (bank active mode: PRE + ACT + WRITE command, different row address, WTRCD = 0 cycles, TRWL = 0 cycles) RZ/T2L Datasheet 2. Electrical Characteristics R01DS0409EJ0130 Rev.1.30 Feb 27, 2026 Page 61 of 103 |
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