RZSLASHT2L datasheet(34/103 Pages) RENESAS

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Table 2.16

Ethernet PHY reference clock output timing

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

ETHn_REFCLK cycle time

tCK

—

ETHn_REFCLK frequency

—

25.00 ± 50 ppm

MHz

EtherCAT in use

25.00 ± 25 ppm

MHz

ETHn_REFCLK duty

—

ETHn_REFCLK rising/falling time

tCKr / tCKf

—

0.5

—

4.0

RMIIn_REFCLK cycle time

tCK

—

RMIIn_REFCLK frequency

—

50.00 ± 50 ppm

MHz

RMIIn_REFCLK duty

—

RMIIn_REFCLK rising/falling time

tCKr / tCKf

—

0.5

—

3.5

ETHn_REFCLK

RMIIn_REFCLK

output

tCK

1/2 VCC1833_n

tCKf

tCKr

VOH

VOL

1/2 VCC1833_n

VOL

VOH

Figure 2.3

Ethernet PHY reference clock output timing

2.5.1.3

EXTCLKIN External Clock Input

Table 2.17

EXTCLKIN clock timing

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

EXTCLKIN external clock frequency

fEXTCLKIN

—

25.00 ± 50 ppm

MHz

EtherCAT in use

25.00 ± 25 ppm

MHz

EXTCLKIN duty

rEXTCLKIN

—

±5%

—

EXTCLKIN rising time

trEXTCLKIN

—

EXTCLKIN falling time

tfEXTCLKIN

—

Note:

When using crystal resonator (i.e. EXTAL/XTAL clock is used), EXTCLKIN should be driven low.

EXTCLKIN external clock input

1/2 × VCC33

fEXTCLKIN

VIH33

VIL33

frEXTCLKIN

ffEXTCLKIN

Figure 2.4

EXTCLKIN external clock input timing

RZ/T2L Datasheet

2. Electrical Characteristics

R01DS0409EJ0130 Rev.1.30

Feb 27, 2026

Page 34 of 103

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