RZSLASHT2L datasheet(11/103 Pages) RENESAS

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1.3

Block Diagram

Figure 1.1 shows a block diagram.

Peripheral modules for Non-Safety

Peripheral modules for Motor

Subsystem

On-chip extended

SRAM

with ECC

xSPI × 2

channels

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port 10

Port 11

Port 12

Port 13

Port 14

Port 15

Port 16

Port 17

Port 18

Port 19

Port 20

Port 21

Port 22

Port 23

Clock

generation

circuit

BSC

ESC × 3 ports

TFU

CANFD × 2 channels

WDT × 1 channels

POEG (unit 0)

CMT × 6 channels (unit 0-2)

CMTW × 2 channels (unit 0-1)

POE3

12-bit A/D converter (unit 0-1)

MTU3

GPT × 7 channels (unit 0)

DSMIF × 6 channels (unit 0-1)

SCI × 5 channels

GMAC

: Ethernet MAC

ETHSW

: Ethernet switch

ESC

: EtherCAT slave controller

DMAC

: DMA controller

BSC

: Bus state controller

xSPI

: Expanded serial peripheral interface

WDT

: Watchdog timer

SCI

: Serial communication interface

SPI

: Serial peripheral interface

USB

: USB 2.0 HS host/function module

GIC

: Generic interrupt controller

MPU

: Memory protection unit

ELC

: Event link controller

MTU3

: Multi-function timer pulse unit 3

SHOSTIF

: Serial host interface

MBXSEM

: Mailbox and Semaphore

GPT

: General PWM timer

CMT

: Compare match timer

CMTW

: Compare match timer W

POE3

: Port output enable 3

POEG

: Port output enable for GPT

RTC

: Real time clock

IIC

: I2C bus interface

CANFD

: CANFD module

DSMIF

: ΔΣ interface

TFU

: Trigonometric function unit

CRC

: CRC (cyclic redundancy check) calculator

CLMA

: Clock monitor circuit

DOC

: Data operation circuit

TSU

: Temperature sensor unit

OTP

: One-time programmable memory

TSU

Port 24

TCM

Cortex-R52

(CPU0)

GIC

MPU

GMAC × 1 port

USB

× 1 port

DMAC ×

16 channels

(unit 0)

DMAC ×

16 channels

(unit 1)

GPT × 7 channels (unit 1)

POEG (unit 1)

IIC × 2 channels

SPI × 3 channels

CRC (unit 0)

DOC

Peripheral modules for Safety

GPT × 4 channels (unit 2)

POEG (unit 2)

RTC

CRC (unit 1)

SCI × 1 channel

IIC × 1 channel

SPI × 1 channel

CLMA

ELC

MBXSEM

OTP

Security

Encoder interface Subsystem

A-format × 2 channels

HIPERFACE DSL × 2 channels

ENCOUT × 1 channels

EnDat 2.2 × 2 channels

BiSS-C × 2 channels

SHOSTIF

Figure 1.1

Block diagram

RZ/T2L Datasheet

1. Overview

R01DS0409EJ0130 Rev.1.30

Feb 27, 2026

Page 11 of 103

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