AMD-K6-2ESLASH400AMZ datasheet(197/332 Pages) AMD

197 / 332 page

Chapter 7

Power-On Configuration and Initialization

179

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

Power-On Configuration and Initialization

On power-on, the system logic must reset the AMD-K6-2E

processor by asserting the RESET signal. When the processor

samples RESET asserted, it immediately flushes and initializes

all internal resources and its internal state, including its

pipelines and caches, the floating-point state, the MMX and

3DNow! states, and all registers. Then, the processor jumps to

address FFFF_FFF0h to start instruction execution.

7.1

Signals Sampled During the Falling Transition of RESET

FLUSH#

FLUSH# is sampled on the falling transition of RESET to

determine if the processor begins normal instruction execution

or enters three-state test mode.

If FLUSH# is High during the falling transition of RESET,

the processor unconditionally runs its Built-In Self Test

(BIST), performs the normal reset functions, then jumps to

address FFFF_FFF0h to start instruction execution. (See

“Built-In Self-Test (BIST)” on page 227 for more details.)

If FLUSH# is Low during the falling transition of RESET,

the

processor

enters

three-state

test

mode.

(See

“Three-State Test Mode” on page 228 and “FLUSH# (Cache

Flush)” on page 104 for more details.)

BF[2:0]

Th e i n te rnal o p e ra t ing frequency of the pro c ess o r i s

determined by the state of the bus frequency signals BF[2:0]

when they are sampled during the falling transition of RESET.

The frequency of the CLK input signal is multiplied internally

by a ratio defined by BF[2:0]. (See “BF[2:0] (Bus Frequency)”

on page 93 for the processor-clock to bus-clock ratios.)

AMD-K6-2E/400AMZ Datasheet(PDF) 197 Page - Advanced Micro Devices

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