AMD-K6-2ESLASH400AMZ datasheet(208/332 Pages) AMD

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190

Cache Organization

Chapter 8

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

Cache-Related Signals

Complete descriptions of the signals that control cacheability

and cache coherency are given on the following pages:

CACHE#—page 97

EADS#—page 101

FLUSH#—page 104

HIT#—page 105

HITM#—page 105

INV—page 110

KEN#—page 111

PCD—page 115

PWT—page 117

WB/WT#—page 129

8.4

Cache Disabling and Flushing

To completely disable all cache accesses, the CD bit must be set

to 1 and the cache must be completely flushed. There are three

different methods for flushing the cache. The first method

relies on the system logic, and the other two rely on software.

For the system logic to flush the cache, the processor must

sample FLUSH# asserted. In this method, the processor

writes back any data cache lines that are in the Modified

state, invalidates all lines in the instruction and data caches,

and then executes a flush acknowledge special cycle (See

Table 23 on page 132).

The second method relies on software to execute the

WBINVD instruction which causes all modified lines to first

be written back to memory, then marks all cache lines as

invalid. Alternatively, if writing modified lines back to

memory is not necessary, the INVD instruction can be used

to invalidate all cache lines.

The third method is to make use of the Page Flush/Invalidate

optional flushing of a specific 4-Kbyte page from the linear

address space (see “Page Flush/Invalidate Register (PFIR)”

on page 200). Unlike the previous two methods of flushing

the cache, this particular method requires the software to be

aware of which specific pages must be flushed and

invalidated.

AMD-K6-2E/400AMZ Datasheet(PDF) 208 Page - Advanced Micro Devices

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