AMD-K6-2ESLASH400AMZ datasheet(234/332 Pages) AMD

234 / 332 page

216

Floating-Point and Multimedia Execution Units

Chapter 10

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

10.3

Floating-Point and MMX™/3DNow!™ Instruction Compatibility

Registers

The eight 64-bit MMX registers (which are also utilized by

3DNow! instructions) are mapped on the floating-point stack.

This enables backward compatibility with all existing software.

For example, the register saving event that is performed by

operating systems during task switching requires no changes to

the operating system. The same support provided in an

operating system’s interrupt 7 handler (Device Not Available)

for saving and restoring the floating-point registers also

supports saving and restoring the MMX registers.

Exceptions

There are no new exceptions defined for supporting the MMX

and 3DNow! instructions. All exceptions that occur while

decoding or executing an MMX or 3DNow! instruction are

handled in existing exception handlers without modification.

FERR# and IGNNE#

MMX instructions and 3DNow! instructions do not generate

f l oating-p oint e x ceptions. Ho w e v e r, if an unm aske d

floating-point exception is pending, the processor asserts

FERR# at the instruction boundary of the next floating-point

instruction, MMX instruction, 3DNow! instruction or WAIT

instruction.

The sampling of IGNNE# asserted only affects processor

ope rat io n during t h e e x ec ut ion of an er ro r-sensi t ive

flo a ting-p oint ins t ructi o n, M M X ins t ructio n, 3 DNow!

instruction or WAIT instruction when the NE bit in CR0 is

cleared to 0.

AMD-K6-2E/400AMZ Datasheet(PDF) 234 Page - Advanced Micro Devices